Author ORCID Identifier
https://orcid.org/0000-0002-2549-5092
Biosketch
Mr R.Vijay Sai is presently associated with School of Computing, Sastra Deemed University, Tanjore, as Assistant Professor. He is a dedicated academician and researcher with a strong passion for teaching, student mentoring, and continuous learning. He is deeply committed to creating an engaging and supportive learning environment for students. His calm personality, dedication to education, and willingness to help others, make him respected among students and colleagues alike. He aspires to inspire future generations through knowledge, compassion, and lifelong learning.
He has published more than twenty research papers in various peer-reviewed journals. His areas of academic interests include cryptography and network security, computer architecture, cache memory security, data communication, computer networks, digital CMOS VLSI design and digital system design, that bridge theory with practical applications. His hobbies include writing English poems, addressing various social issues and remedies to solve them. Quote writing is also his favorite interest. Traveling and exploring places provide him happiness and peace.
Date of Award
17-8-2025
Document Type
Thesis
School
School of Computing
Programme
Ph.D.-Doctoral of Philosophy
First Advisor
Dr.Har Narayan Upadhyay
Keywords
Undeviating Adaptive Sheltered Cryptography, Cache Memory, Field Programmable Gated Array, Data Scrambling, Security in Memory
Abstract
Semiconductor technology is growing very rapidly in their architectural developments, involving the usage of processor and memory. Presence of memory, in general is a vital commodity in various devices which are almost embedded into human activity, from robust work stations to handy mobile phones. Security of data stored in memory is very important, and hence, observation must be made that these valuable data should not be thwarted by malicious means. Security in cache memory is a major issue in memory related applications such as smart cards and bio-metric implementations.
Cache, is a small and limited memory located between central processing unit and main memory unit. When the significance of caches is growing, security in cache memory and the need of cryptographic exploitation into it, becomes important. Some of the challenges in design of cache architecture are algorithm efficiency, technology focus, hardware complexity, power consumption, data retrieval efficiency and security aspects. Hence, the specific objective of this research is to design a cache memory with good security, providing optimum power consumption as well as occupying less area.
The research works concentrates on scrambling based algorithm, which is based on shuffling data bits by applying logical xor operation over a variable bit pattern and encrypting and decrypting it, as well as using the concept of substitution box in AES algorithm and making it as dynamic to enhance data security and also works on designing a dual field Vedic multiplier based on look up table carry select adder, which is made secure by techniques of elliptic curve cryptography. The proposed work focuses on analyzing power related parameters, such as power dissipation and power consumption, but does not concentrates on shielding against power attacks and timing attacks. AES implementations can be vulnerable to cache- based timing and power side-channel attacks, though the core algorithm itself remains cryptographically secure. These attacks exploit indirect leakage from cache memory usage patterns during encryption. Results based on the application of these techniques show good responses when compared with the existing methodologies.
Recommended Citation
R, Vijay Sai Mr, "Investigations of Secure Memory for VLSI Based Crypto System" (2025). Theses and Dissertations. 205.
https://knowledgeconnect.sastra.edu/theses/205